Browse Prior Art Database

On-Chip Clocking of Power Supply

IP.com Disclosure Number: IPCOM000049083D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Gheewala, TR: AUTHOR

Abstract

A circuit is described for on-chip clocking of a power supply for Josephson circuits. The supply voltage is reduced to zero in a periodic manner without the need for AC power distribution and on-chip clipping. This results in improved cycle time, dwell. and lower on-chip power dissipation. Also, the supply voltage can be adjusted to compensate for chip-to-chip variations in I(o) and R. The Josephson load devices on the circuit chip are shunted by a series of non-latching Josephson devices which are controlled by an AC control current.

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On-Chip Clocking of Power Supply

A circuit is described for on-chip clocking of a power supply for Josephson circuits. The supply voltage is reduced to zero in a periodic manner without the need for AC power distribution and on-chip clipping. This results in improved cycle time, dwell. and lower on-chip power dissipation. Also, the supply voltage can be adjusted to compensate for chip-to-chip variations in I(o) and R. The Josephson load devices on the circuit chip are shunted by a series of non- latching Josephson devices which are controlled by an AC control current.

Fig. 1 shows a circuit in which a plurality of load devices 1. 2. ...M are
powered by a DC source V(dc) which is shunted by a series 1, 2, ...N of non- latching Josephson devices (e. g., shaped junctions). Fig. 2 shows the waveforms used to provide on-chip clocking, including the voltage waveform V(s) to the load devices, the control current I(c), and the threshold curve 10/s/ of the non-latching junctions.

The non-latching junctions are reset to the zero voltage state every time the sinusoidal control current I(c) crosses zero. This interrupts the supply current to the load devices and allows the latching circuits to reset. The dwell of the power supply is determined by the amplitude of the control current. The rise and fall times are determined by the dynamics of the non-latching junctions and are extremely fast compared to circuits where the rise and fall times are determined by the frequency response of the cables, the transformers, and the power efficiency of regulator devices.

The non-latching devices do not need to be good quality tunnel junctions. They can easily be non-hysteretic, "weak-link" like junctions. Further, very little power is dissipated in the non-latching junctions.

The c...