Browse Prior Art Database

Interdigitated Memory Accessing Circuit

IP.com Disclosure Number: IPCOM000049125D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Pricer, WD: AUTHOR

Abstract

To minimize delays in a memory array using doped polysilicon or substrate diffusion lines, low level interdigitated decoders 10 are interspersed in the array between pairs of polysilicon or diffusion lines 12 and 14 with highly conductive metal accessing lines Y1 and Y2 connected to decoders 10.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 62% of the total text.

Page 1 of 2

Interdigitated Memory Accessing Circuit

To minimize delays in a memory array using doped polysilicon or substrate diffusion lines, low level interdigitated decoders 10 are interspersed in the array between pairs of polysilicon or diffusion lines 12 and 14 with highly conductive metal accessing lines Y1 and Y2 connected to decoders 10.

As indicated in Fig. 1, first and second rows 16 and 18, respectively, of polysilicon or diffusion lines 12 and 14, which may be bit/ sense or word lines, are selectively connected to highly conductive line Y1 through associated decoders 10, with decoders 10 in an even column of decoders being interposed along line Y1 between two adjacent decoders 10 of odd columns of decoders. Line Y2 is similarly connected to third and fourth rows 20 and 22, respectively, of polysilicon or diffusion lines 12 and 14. To implement the low level decoding in this memory-accessing circuit, the lowest order bit pulse used to decode the rows 16, 18, 20 and 22 is replicated and remapped into the array as lines X and X, indicated in Fig. 2. The lines X and X are preferably first level metal lines, although doped polysilicon lines could be used in place of the first level metal lines. This bilateral circuit may be used for applying driving pulses and for input/output data.

The decoder 10, shown in detail in Fig. 2, is used for each of the decoders 10 in the even decoder columns. Each of the decoders 10 in the odd columns uses a similar decoder but with the...