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20-Bit Synchronous Binary Counter with Automatic Load and Synchronous Carry

IP.com Disclosure Number: IPCOM000049126D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Conti, D: AUTHOR [+2]

Abstract

This article discloses a 50 megahertz, 20-bit synchronous binary counter that can also be used as a 20-bit shift register or a 20-bit D latch.

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20-Bit Synchronous Binary Counter with Automatic Load and Synchronous Carry

This article discloses a 50 megahertz, 20-bit synchronous binary counter that can also be used as a 20-bit shift register or a 20-bit D latch.

This desirable result is achieved by supplying the counter with a feedback circuit containing a synchronous carry logic circuit and an automatic load logic circuit together with three different input clocks A, B and C. The A and B clocks are used when the device is acting as a shift register, and the B and C clocks are used when the device is acting as a counter or a latch. All the clocks are phased in order to guarantee that RACE conditions cannot occur and the carry as well as the 20 output bits all change on the B clock's leading edge.

This counter is synchronously and automatically loaded whenever the carry logic provides an output carry signal to the automatic load logic circuit and the manual load enable input to the automatic load circuit is at a logic "1" state. One clock period is required for the automatic loading sequence. Normally the system clocks are continuous at the input pins. When the count enable inputs to the synchronous carry logic are high and a carry signal appears, the device will automatically load data on the data in bus into the counter and one period later the device will count up from the loaded value. Thus the device in this mode is an N + 1 divider, where N is any value between 1 220.

If the manual load enable input t...