Browse Prior Art Database

Compact Low Profile VLSI IC Package

IP.com Disclosure Number: IPCOM000049134D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Gresko, AR: AUTHOR

Abstract

Assembly 10 is a compact low profile configured package for an integrated circuit (IC) module with high density input/output interconnections. It is particularly useful for very large-scale integration (VLSI) applications.

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Compact Low Profile VLSI IC Package

Assembly 10 is a compact low profile configured package for an integrated circuit (IC) module with high density input/output interconnections. It is particularly useful for very large-scale integration (VLSI) applications.

One or more IC chips 1 are carried by interposer 2, which is the same material or which otherwise has thermal characteristics matching those of the material of chip(s) 1. The I/0 terminals (not shown) of the chips 1 are in registration with and bonded to central I/O pads (not shown) of interposer 2 by solder reflow bonds 3. The I/O pads are part of a fan-out pattern of ultra-fine (UF) conductors (not shown) on the top surface of (or layered within the) interposer 2. The UF conductors are selectively extended to a pair of opposite edges of interposer 2. There, the conductors are terminated as peripheral I/O termination sites (not shown) on the top surface of the interposer 2. The peripheral termination sites are arranged in multiple, e.g., three, parallel rows A, B, C, each row having a number of sites.

The assembly 10 includes a flexible flat printed circuit (PC) multiconductor cable or tape 4, which has a corresponding number, i.e., three, of multiple PC conductor planes or levels a, b, c. The ends of the cable conductors of levels a, b, and c, respectively, are in register with and bonded to the peripheral termination sites of rows A, B, and C, respectively, by microsurface welding or the like.

The fragile...