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Stuck At 0 Or At 1 Check Circuit

IP.com Disclosure Number: IPCOM000049139D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Dutton, PF: AUTHOR

Abstract

This arrangement provides a check for a line that is stuck at a value of "1" or "0", without using parity or duplexing a line. This problem is very common in control circuitry where it becomes very difficult to generate parity over a number of control lines, because these generally do not have the same timing and are not located in the same control circuitry. Also, because of I/O limitations it becomes impractical to duplex all of the control lines.

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Stuck At 0 Or At 1 Check Circuit

This arrangement provides a check for a line that is stuck at a value of "1" or "0", without using parity or duplexing a line. This problem is very common in control circuitry where it becomes very difficult to generate parity over a number of control lines, because these generally do not have the same timing and are not located in the same control circuitry. Also, because of I/O limitations it becomes impractical to duplex all of the control lines.

This circuit is able to check for a stuck at 0 or stuck at 1 condition in an associated signal line, from the line driver's point of view, without adding any extra input/output elements.

Fig. 1 shows a control signal line extending between a first module A and a second module B. In module A, there is provided a chip which contains a driver 3 which supplies a signal to a module I/O terminal 5, where a control signal line 7 extends to module B to the module input/output terminal 9 to a receiver 11 mounted on a chip in module B. Lines stuck at 1 or 0 which are caused by package failures, such as opens or shorts in the chip or module, are among the most difficult circuit failures to detect and have relatively high failure rates.

Fig. 2 shows the checking circuit in one preferred form. The output signal is supplied on a line 1 through the bidirectional driver 3 from which a signal of the same polarity is supplied to I/O terminal 5. Another output line 13 from driver 3 is supplied to one inp...