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Planarization of Insulators for Submicron Multi-Level Structures

IP.com Disclosure Number: IPCOM000049148D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Agnihotri, RK: AUTHOR [+2]

Abstract

A process of making planar metal and insulator is described for interconnecting a dense integrated circuit.

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Planarization of Insulators for Submicron Multi-Level Structures

A process of making planar metal and insulator is described for interconnecting a dense integrated circuit.

In Fig. 1, semiconductor substrate 1 has a first metal (Approximately 1 Mu thick) layer 2 and a polyimide layer 3 (Approximately 1 Mu m). A polyimide layer about 7-10 Mu m in thickness. Polyimide 4 may be substituted with other coatings like a photoresist. All organic coatings are cured to 300- 450 degrees
C.

A reactive ion etch in O(2) is performed to etch the layer 4 and 3 such that the metal 2 is barely exposed.

In Fig. 2, a thin layer of silicon nitride 5 (100-200 Angstroms) is put on a resist overhang 6 is made using known techniques, and the silicon nitride is etched using CF plasma to expose the top of the metal 2. Then, a metal stud 7 is deposited on the top of metal 2 and resist overhang 6.

Fig. 3 shows the structure after lift-off of layer 6.

The process is repeated to achieve a multi-level metal interconnection.

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