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2R 1W Static RAM Cell

IP.com Disclosure Number: IPCOM000049164D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Chin, WB: AUTHOR [+2]

Abstract

Three port RAMs (random-access memories) with two read ports and one write port are needed for many processor designs. The conventional implementation of the two read port functions uses two sets of output devices in the RAM cell, and two sets of word lines, bit lines and the associated drivers and sensing circuits. It was proposed that one set be used to provide the two port functions. Extra voltage levels are introduced by the read word line to indicate whether it is selected by port 1 or port 2 or by both. Extra bit line output voltage levels are generated to carry two bits of information, for port 1 bit and port 2 bit. This article illustrates the ideas with a design of a three-port RAM with an organization of 64 x 18.

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2R 1W Static RAM Cell

Three port RAMs (random-access memories) with two read ports and one write port are needed for many processor designs. The conventional implementation of the two read port functions uses two sets of output devices in the RAM cell, and two sets of word lines, bit lines and the associated drivers and sensing circuits. It was proposed that one set be used to provide the two port functions. Extra voltage levels are introduced by the read word line to indicate whether it is selected by port 1 or port 2 or by both. Extra bit line output voltage levels are generated to carry two bits of information, for port 1 bit and port 2 bit. This article illustrates the ideas with a design of a three-port RAM with an organization of 64 x 18.

An overview is shown in Fig. 1. Read/write controls are not shown to simplify the explanation.

The read word line driver (RWLD) is shown in Fig. 2. RWLD can generate four discrete voltage levels. The lowest level (approximately GND) is the standby level. The other three levels are to gate the read currents through the output device of the memory cell. The highest level (Approximately V) corresponds to simultaneous select of the word line by both port 1 address and port 2 address.

One sensing scheme is shown in Figs. 3, 4 and 5.

Four possible voltage levels can be generated on the read bit line, which are to be sensed and translated into two bits. The exact levels are mainly determined by the value of RL and the Beta of the...