Browse Prior Art Database

Three Port RAM Design with Two RAM Cells

IP.com Disclosure Number: IPCOM000049165D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Chin, WB: AUTHOR [+2]

Abstract

For a three-port RAM (random-access memory) with two read ports and one write port, two sets of read word line and read bit lines are generally required for each cell (Fig. 1). This article proposes a three-port RAM with only one set of bit line(s) and word line per cell (Fig. 2).

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Three Port RAM Design with Two RAM Cells

For a three-port RAM (random-access memory) with two read ports and one write port, two sets of read word line and read bit lines are generally required for each cell (Fig. 1). This article proposes a three-port RAM with only one set of bit line(s) and word line per cell (Fig. 2).

Word line circuits will have to be able to produce multiple levels for rear: WLO Unselected

WL1 Selected by port 1 address

WL2 Selected by port 2 address

WL3 Selected by both port 1 and port 2

Bit lines are also set at different levels according to the levels of word line selection: BL): #Bi=0; Bj=0(see original) Bi = 0; Bj = 0

BL1: Bi = 1; Bj = 0

BL2: Bi = 0; Bj = 1

BL3: Bi = 1; Bj = 1

The sense amplifier SAl2 will have to encode these bit levels into RB1 and RB2.

VR2 is between BL1 and BL2; V1 is between BL(see original) and BL1; VR1 is RB2 = (see original); V1+VR2 if RB2 = 1.

This is illustrated as follows:

RB2 # RB1

BL0# 0 0

V1-----------> BL1 0 1

VR2----------> BL2 1 0

V1 VR2-------> BL3 1 1

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