Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Latch Element Design

IP.com Disclosure Number: IPCOM000049167D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Graf, MC: AUTHOR

Abstract

Designing for testability is an objective of most LSI/VLSI product designers. Designs that follow scan path testing strategies, i.e., LSSD (Level Sensitive Scan Design) (*), call for the use of shift register latches (SRLs) to observe and/or control nodes internal to a machine. This document describes a method of physically implementing an SRL for use in testing and diagnosing the product.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Latch Element Design

Designing for testability is an objective of most LSI/VLSI product designers. Designs that follow scan path testing strategies, i.e., LSSD (Level Sensitive Scan Design) (*), call for the use of shift register latches (SRLs) to observe and/or control nodes internal to a machine. This document describes a method of physically implementing an SRL for use in testing and diagnosing the product.

Today, most SRLs, comprised of Ll and L2 latches, are built out of logic gates, as shown in Figs. 1 and 2. This type of implementation offers versatility in design and application but requires substantial power and silicon area. Other SRL realizations are custom designed for a particular application. Here, generalization of use is sacrificed for less power and silicon area. Modification of the custom design to add additional clocked ports may be difficult. Fig. 3 shows an example of an L1 latch that is custom designed. The latch element, that is described here, is a primitive building block, as is the NAND gate, from which a multitude of latch configurations can be derived. The net result is a method of latch design that offers versatility, as does the logic gate latch implementation, yet consumes less in power and silicon area, comparable to a custom-designed latch.

A block diagram of the latch element (LE) is shown in Fig. 4.

The LE has a minimum of three inputs, Clock (CL), Data-In (DI) and Feedback (FB). Clock and Data-In must be implemented to accept normal interconnection levels, Feed-back is an SRL internal node and is therefore not as constrained. As an option, the LE may accept m...