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Browse Prior Art Database

High Speed Virtual FIFO Memory

IP.com Disclosure Number: IPCOM000049179D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Tast, HW: AUTHOR

Abstract

A so-called FIFO (first-in, first-out) memory consists of a register chain. A data word is written into the first register of the chain, setting an associated note bit. If this note bit is not active for the second register of the chain, a data word is transferred from the first to the second register, erasing the note bit of the first register. In this manner, the data word moves down the register chain until it reaches an occupied register. The data word written in first moves straight to the output of the FIFO memory. The disadvantage of known FIFO memories is that their capacity is rather limited and that any capacity increase leads to excessive fall through times, making such memories unsuitable for practical use.

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High Speed Virtual FIFO Memory

A so-called FIFO (first-in, first-out) memory consists of a register chain. A data word is written into the first register of the chain, setting an associated note bit. If this note bit is not active for the second register of the chain, a data word is transferred from the first to the second register, erasing the note bit of the first register. In this manner, the data word moves down the register chain until it reaches an occupied register. The data word written in first moves straight to the output of the FIFO memory. The disadvantage of known FIFO memories is that their capacity is rather limited and that any capacity increase leads to excessive fall through times, making such memories unsuitable for practical use. AB Therefore, a virtual FIFO memory is proposed in which the data words no longer move down the register chain. Instead, the stored data words are permanently stored and only seemingly shifted. For this purpose, the illustrated circuit arrangement is used in which a write address pointer points at an address of a read/write storage into which the next word is to be written. After each write step, the pointer is changed in a particular sequence. In addition, there is a read address pointer pointing at the next word to be read from the read/write storage. The read address pointer starts with the address of the word written in first and follows the write address pointer as reading proceeds. As a result, the data remain p...