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Checking Of Tristate Drivers

IP.com Disclosure Number: IPCOM000049181D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Blum, A: AUTHOR

Abstract

Fig. 1 shows a tristate driver (TSD) circuit which, together with a plurality of other TSDs, is connected to a dotted bus. For putting binary ones or zeros on the bus, a data-in signal is applied to AND gate 1, making transistor T2 or T3 conductive. When one TSD puts data on the bus, the other TSDs have to be switched to a high-impedance (HI) state. This is done by control signal FHI which is one for the respective TSD and applied to inverter 2, thus acting on transistors T1 and T4. For all other TSDs, signal FHI is zero.

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Checking Of Tristate Drivers

Fig. 1 shows a tristate driver (TSD) circuit which, together with a plurality of other TSDs, is connected to a dotted bus. For putting binary ones or zeros on the bus, a data-in signal is applied to AND gate 1, making transistor T2 or T3 conductive. When one TSD puts data on the bus, the other TSDs have to be switched to a high-impedance (HI) state. This is done by control signal FHI which is one for the respective TSD and applied to inverter 2, thus acting on transistors T1 and T4. For all other TSDs, signal FHI is zero.

TSDs can be damaged when T2 and T3 are respectively conductive in a first and a second TSD for longer than a small overlapping time.

To check if T2 or T3 is stuck in a conductive state, several methods can be used. According to Fig. 1. two supplementary transistors T5 and T6 together with a resistor Rl are provided. In the high-impedance state, neither T5 nor T6 must be conductive, so that the signal at output 3 has a positive polarity when signal FHI is active.

Fig. 2 shows a different method. N data units together with their TSDs are connected to the dotted bus which is also connected to the receiver REC of a further common unit M, such as a memory. Transmission of data between data units and unit M is controlled by a bus-valid (BV) signal giving control to one of the data units and by a data-valid (DV) signal permitting transmission of data on the bus. Between signals BV and DV, there are idle times which are used to check the TSDs. Unit M is provided with means for detecting the high...