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FET Dottable Active Drain Stage

IP.com Disclosure Number: IPCOM000049187D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 27K

Publishing Venue

IBM

Related People

Sohn, DT: AUTHOR

Abstract

An output stage of an integrated MOSFET (metal-oxide semiconductor field-effect transistor) off-chip driver has an active FET and a load FET in a conventional push-pull configuration, and it includes two additional FETs that permit the stage to be connected with similar stages in a wired or dot NOR configuration and also provide turn on and turn off times that are comparable to a push-pull stage. The circuit can be used as a replacement for an open drain stage or a push-pull stage.

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FET Dottable Active Drain Stage

An output stage of an integrated MOSFET (metal-oxide semiconductor field- effect transistor) off-chip driver has an active FET and a load FET in a conventional push-pull configuration, and it includes two additional FETs that permit the stage to be connected with similar stages in a wired or dot NOR configuration and also provide turn on and turn off times that are comparable to a push-pull stage. The circuit can be used as a replacement for an open drain stage or a push-pull stage.

An open drain stage is an FET with its drain terminal open circuited. When drain terminals of other open drain stages are wired together with a pull-up resistor, the circuit produces a positive NOR function. Load current is supplied through the pull-up resistor. Push pull stages can not be used in wired logic functions because when two connected stages are in opposite states, they form a short circuit. This circuit permits a wired NOR connection in a modified push- pull stage.

Q1 and Q2 have their gate terminals connected to opposite phases of an input signal as in a conventional push-pull stage. Q3 has a width over length ratio matched to that of a load device and is connected between Ql and Q2 to function as a semi-load device. Q4 connects the gate of Q3 to the input through the source to drain circuit of Q4, and Q4 has its gate connected to the power supply terminal so that it applies the input to the gate of Q3 except for a time delay.

The following table shows the states of the FETs when the input signal is up and down and rising or falling. The rising and falling transitions represent a time when Q1 and Q2 have both switched but Q...