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Browse Prior Art Database

Simplified Polysilicon/ Silicide Process and Structure

IP.com Disclosure Number: IPCOM000049204D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Soderman, DA: AUTHOR

Abstract

A simplified process is disclosed for forming an FET device having silicide converted polycrystalline silicon structures. The simplified seven-mask process provides an enhanced diffusion to polycrystalline silicon low resistance contact by incorporating a silicide interface layer therebetween.

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Simplified Polysilicon/ Silicide Process and Structure

A simplified process is disclosed for forming an FET device having silicide converted polycrystalline silicon structures. The simplified seven-mask process provides an enhanced diffusion to polycrystalline silicon low resistance contact by incorporating a silicide interface layer therebetween.

The sequence of Figs. 1A through lG illustrates the steps in the formation of the FET device. Fig. 1A illustrates the first step wherein layers of silicon dioxide 2 and silicon nitride 4 are deposited on the surface of the 10-100 ohm centimeter p-type silicon substrate 1. A first photolithographic mask is employed to define the etching of a silicon nitride layer 4 and the selective area for the channel stop formed by a field implantation of boron ions 6, as shown in Fig. 1A. This step is followed by growing a approximately 5000 Angstroms thick recessed oxide (ROX) region 8 for device isolation, as shown in Fig. 1B. Upon subsequent removal of the remaining silicon nitride 4 and oxide 2; the 400-1000 Angstroms gate oxide 5 is grown. A boron ion implant 10 may be employed to adjust the threshold voltage of enhancement-type FET devices.

A second positive photolithographic mask 12 is used for selective phosphorus or arsenic ion implantation to dope part of the source and drain areas 14 of the FET devices located adjacent to the device channels which form part of the structure and-are used to create the low resistance n+ diffusion/silicide interconnection wiring rails. This partial structure is shown in Fig. 1C.

A third negative photolithographic mask 16 deposited over the second photoresist layer 12 is used to define the oxide etching of buried polysilicon to n+ diffusion contact window above source and drain areas 14 and, in addition, forms a lift-off structure after the positive resist 12 is undercut by additional light exposure and continued development, as shown in Fig. 1D. Optionally, channel areas of depletion-type FET devices are covered by only the negative resist 16, while the channel region 9 of the enhancement FET device shown is covered by both resist layers 12 and 16. Thus the combination of two masks is used to create a third pattern without requiring another photolithographic mask.

A thin layer 17 of palladium, platinum, or tungsten 500-2000 thick is co- evaporated with silicon over the surface. The unwanted material is "lifted-off" along with the resist layers 12 and 16. After sintering, the remaining material of layer 17 forms the low resistance silicide layer 17 shown in Fig. 1E.

A polycrystalline silicon layer 20 is deposited and can be either very lightly doped n-type, allowing high resistance poly resistors 20" or heavily doped by in situ POCl(3)/ion implantation for standard processing. A fourth photolithographic mask is used to define the shape of polysilicon layer 20 for the gate 20' of the FET device and associated wiring. The initial silicide wind...