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Bidirectional Interface Test System

IP.com Disclosure Number: IPCOM000049210D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Jones, DF: AUTHOR [+2]

Abstract

An improved method of stress testing a device that communicates over a digital interface by modification of timing relationships is provided.

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Bidirectional Interface Test System

An improved method of stress testing a device that communicates over a digital interface by modification of timing relationships is provided.

A digital interface is dependent upon the timing relationships between signals, duration of individual signals, and voltage amplitude of the signals. The test system is inserted between two devices communicating through a digital interface. Each signal path allows timing modification (delay of a signal), error injection, and output amplitude control (via open collector drivers). Signal paths may be selected as unidirectional or bidirectional. Bidirectional signal paths are created by combining two unidirectional lines. This permits separate adjustment of delay in each direction. These parameters are controlled via an external microprocessor.

The overall data flow (unidirectional) is shown in Fig. 1.

Each signal path contains three programmable delay modules in series. This provides a programmable delay of up to 1023 ns in 1 ns increments. An unbuffered output is provided after the delay lines to provide a trigger signal to any external error injection device.

The error injection logic will permit a positive signal to invert the output signal for the duration of the error signal. The final logic stage is an open collector 60 ma driver, which provides the ability to operate in a bidirectional mode.

In the unidirectional mode (MODE='0') (Fig. 2) the input NAND gates N1, N2 outputs are high, enabling the output buffers 01, 02 and delay modules D1, D2. The Mode relay R is disabled, opening both contacts. The imput signal will pass from the input nodes A and B through the delay gates and output drivers to the output nodes A' and B'. Both sides operate independently of the other.

When the MODE line (Fig. 2) is high, the tw...