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Load Alternate Pooled I/O Registers

IP.com Disclosure Number: IPCOM000049213D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 22K

Publishing Venue

IBM

Related People

Hammer, WE: AUTHOR [+2]

Abstract

An alternate set of shared data IORs (I/O registers) eliminates the need for unique IORs. The I0R requirement is reduced from 80 to 40 for the full eight-arm complement of a direct-access storage device (DASD).

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Load Alternate Pooled I/O Registers

An alternate set of shared data IORs (I/O registers) eliminates the need for unique IORs. The I0R requirement is reduced from 80 to 40 for the full eight-arm complement of a direct-access storage device (DASD).

The current implementation of the IBM System/38 allows an I/O adapter to signal the channel to load a set of shared data IORs with a Load Multiple Register Channel Control Field (CCF). This allows a single adapter to control several direct-access file arms in a serial fashion and these arms to share data IORs. Commands are issued by the CPU (Central Processing Unit) to each of these arms and the first arm to RPS (Rotational Position Sense) hit requests the CPU to load the addresses associated with this arm into the shared data IORs vie the Load Multiple Register CCF. If an error should occur during this arm's read/write operation (ECC check, channel overrun, etc), the adapter will internally perform error recovery, without CPU involvement, by taking an extra revolution before retrying. Since the data I0Rs are shared, with the prior arrangement no other arm controlled by the same adapter can transfer data during this error recovery time because its Load Multiple Register CCF would destroy the data IOR addresses of the arm in error recovery.

The present arrangement allows for the other arms controlled by the same adapter to transfer data during the error-recovery time through the use of an alternate set of shared data IORs. In the case where one arm is involved in error recovery, the other arms which now RPS hit request a Load Multiple Register Alternate Set CCF. This leaves the addresses intact for the arm in error recovery and allows other arms access to memory. Once the error is recovered on the arm in error recovery, all subsequent Load Multiple Register CCFs return to the primary register set. Also, if an error occurs while using the secondary data IORs during error recovery, the primary data IORs are used by other arms.

In the case where two dynamically allocated data paths exist on the same adapter, the first arm to RPS hit would use the primary shared data IORs, if a second arm RPS hits while...