Browse Prior Art Database

Virtual Address Register Integrity

IP.com Disclosure Number: IPCOM000049215D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Kindseth, DM: AUTHOR

Abstract

A virtual address register used for address translation, as described in the IBM Technical Disclosure Bulletin 22, 743 (July 1979) consists of three two-byte registers V0, V1 and V2, where each register is implemented with LSSD (level sensitive scan design) circuitry. The virtual address register is shown in Fig. 4 of the referenced publication. This register is shared by horizontal microcode (HMC) functions and input/ output (I/O), fill instruction buffer (FIB) and timer functions. The frequency of requests for use of the virtual address register by the I/O, FIB and timer functions is relatively small compared to the number of requests by the microprocessor function. The I/O, FIB and timer functions can destroy the contents of the virtual address register if any request breaks in between microprocessor functions.

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Virtual Address Register Integrity

A virtual address register used for address translation, as described in the IBM Technical Disclosure Bulletin 22, 743 (July 1979) consists of three two-byte registers V0, V1 and V2, where each register is implemented with LSSD (level sensitive scan design) circuitry. The virtual address register is shown in Fig. 4 of the referenced publication. This register is shared by horizontal microcode (HMC) functions and input/ output (I/O), fill instruction buffer (FIB) and timer functions. The frequency of requests for use of the virtual address register by the I/O, FIB and timer functions is relatively small compared to the number of requests by the microprocessor function. The I/O, FIB and timer functions can destroy the contents of the virtual address register if any request breaks in between microprocessor functions. In the past this problem was handled by either I/O lockout which can force all I/O, timer and FIB requests out of the VAT (virtual address translation) or by chaining of microprocessor requests which forces priority to be given to the microprocessor. I/O lockout degrades performance and can cause I/O overruns. Chaining can also cause I/O overruns.

The present arrangement eliminates these problems by extending the cycle of the I/O, FIB and timer operations without affecting main storage access time. The cycle extension for these operations does not significantly impact system performance because of their relative infrequency of occurrence. During the disconnect clock cycles of the I/O, FIB and timer operations the contents of the VO and V1 registers are loaded into VAT local storage registers and the contents of the L1 latches of the V2 register are loaded into the L2 latches. A res...