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Instruction Address Sampler

IP.com Disclosure Number: IPCOM000049216D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 6 page(s) / 54K

Publishing Venue

IBM

Related People

Striemer, BL: AUTHOR [+2]

Abstract

Programs executing on computer systems tend to spend most of their time executing a relatively small number of their total instructions. If highly used code segments can be identified, ways can be found to improve overall program performance by improving these segments. A technique that has been used to do this is instruction address sampling. The basic idea is to periodically sample the current instruction address and to accumulate a distribution of address occurrences. This technique has been used on the IBM System/370. The problem with past implementations is the lack of flexibility in sampling rates and the inability to monitor multiple segments of code.

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Instruction Address Sampler

Programs executing on computer systems tend to spend most of their time executing a relatively small number of their total instructions. If highly used code segments can be identified, ways can be found to improve overall program performance by improving these segments. A technique that has been used to do this is instruction address sampling. The basic idea is to periodically sample the current instruction address and to accumulate a distribution of address occurrences. This technique has been used on the IBM System/370. The problem with past implementations is the lack of flexibility in sampling rates and the inability to monitor multiple segments of code.

An Instruction Address Sampling facility is provided for IBM System/ 38 which allows a user to monitor the execution of IMPI (Internal Microprogram Instructions) instructions. The facility is coded in HMC (Horizontal Microcode) for the S/38 CPU (Central Processing Unit). It makes use of interval timer 4 (in the S/38 CPU) and requires the presence of control blocks in the S/38 main store.

The Instruction Address Sampling (IAS) facility allows periodic sampling of the current instruction address and accumulation of a distribution of address occurrences. A contiguous virtual storage range for which this monitoring is to be done is called a counting window. It is divided into equally sized portions called address blocks. Associated with a counting window is a count vector. There is one element in the count vector for each address block. Also associated with each counting window is an out of range counter.

Every time an instruction address is sampled, the IAS determines if the address is within a particular counting window. If it is, the address block that includes the sampled address is determined, and the counter for that block is incremented by one. If the sampled address is not within the window, the out of range counter for that window is incremented.

A wait state counter is also maintained by the IAS. If no task is executing when an address is to be sampled, this counter is incremented.

Interval Timer 4 (IT4) times the period between samples. The current instruction address is sampled each time an exception for IT4 occurs. While sampling is enabled, IT4 is restarted automatically.

The IAS facility is controlled with the instructions Enable Instruction Addressing Sampling (EIAS) and Disable Instruction Address Sampling (DIAS). The sampling parameters are contained in a control block whose address is at offset 'A8'X in the CAT (Control Address Table).

Multiple counting windows can be in use at the same time. When an address is sampled, counts for all windows will be updated. However, the counts for each window are independent of each other.

The IAS control block contains all of the information needed by the IAS facility. The format of the IAS control block is: WAIT STATE COUNTER

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