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Programmable Accurate On-Chip Delay

IP.com Disclosure Number: IPCOM000049227D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 91K

Publishing Venue

IBM

Related People

Landrock, JB: AUTHOR [+4]

Abstract

For generating propagation delays on logic chips which generally consists of logic elementary blocks, such as NAND, NOR, AND, etc., the block delay of one logic elementary block is used. Depending upon the delay required, several such blocks are connected to form a block delay chain.

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Programmable Accurate On-Chip Delay

For generating propagation delays on logic chips which generally consists of logic elementary blocks, such as NAND, NOR, AND, etc., the block delay of one logic elementary block is used. Depending upon the delay required, several such blocks are connected to form a block delay chain.

The disadvantage of such chains is their high tolerance. For a bipolar chip, the typical tolerance is + 70 percent. This tolerance is attributable to differences in the process end operating parameters as well as in the supply voltage.

For generating accurate and programmable propagation delays on the chip in spite of this tolerance, the principle shown in Fig. 1 is used. For this purpose, the number of elementary blocks of a reference block delay chain 1, which are passed in the time gap (CLK phase) between two successive clock pulses, are measured. This information is stored in full in a flip-flop chain 2 at the end of the gap. i.e., at the start of the leading edge of the clock pulse (CLK phase) following the gap. By means of the flip-flop chain thus available as well as by suitable programming and decoding steps, the programmable block delay chain 3 can be programmed to a fixed and accurate propagation delay value. This fixed and accurate value is subsequently available at the start of the next clock pulse cycle.

Control of programming can be effected in each gap or logically at greater intervals. The most accurate propagation delay value is obtained by programming in the CLK phase immediately before the clock cycle in which the delay is required.

By means of a concrete application it will be described below how propagation delays can be set on a logic chip. For this purpose, the following simplifying assumptions are made: a non-inverting AND block is used as an elementary block

block delay = 1 ns (min.)

2 ns (nom.) per block

3 ns (max.)

clock pulse = 20 ns.

The block delay programmed for staggered driver switching is 8 ns. A suitable circuit is shown in Fig. 2. At a minimum block delay of 1 ns and clock pulses of 20 ns, reference block delay chain...