Browse Prior Art Database

High Speed Clock Generation

IP.com Disclosure Number: IPCOM000049258D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

McVey, JM: AUTHOR [+3]

Abstract

Generating clock signals with periods approaching 20 ns requires device with minimal propagation delay. Schottky TTL (transistor-transistor logic) LSI (large-scale integration) parts, such as counters and dividers, have delays which prevent use at this high speed. Clock skew becomes a problem when multiple signals are decoded from the same signal source since delays vary through different signal paths.

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High Speed Clock Generation

Generating clock signals with periods approaching 20 ns requires device with minimal propagation delay. Schottky TTL (transistor-transistor logic) LSI (large-scale integration) parts, such as counters and dividers, have delays which prevent use at this high speed. Clock skew becomes a problem when multiple signals are decoded from the same signal source since delays vary through different signal paths.

This problem is solved using the high speed clock generation circuit shown in Fig. 1 which comprises high speed Schottky J-K flip-flops arranged as a self- correcting 8-bit shift register with a single recirculating bit and a 2-bit binary counter. The correction logic for the shift register comprises three AND gates A1 to A3 which function as a 7-input AND gate connected to the Q outputs of the shift register stages Q0 to Q6. Because of the random states of the shift register stages at power turn-on, a logical "0" is initially supplied to the J input of stage Q0, and this logical "0" is rippled through the shift register by subsequent clock pulses to initialize the shift register. Once the shift register is initialized, the correction logic produces a logic "1" which is provided at the J input of stage Q0 and thereafter with every eighth clock pulse. The J-K flip-flops DO and D1 are connected to function as a 2-bit binary counter. The timing diagrams for the 8-bit shift register and the 2-bit counter are shown in Fig. 2.

Each bit of the...