Browse Prior Art Database

Priority Arbiter

IP.com Disclosure Number: IPCOM000049259D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Lee, RC: AUTHOR [+2]

Abstract

A normal service request/grant protocol between a processor and a device is always on a one to one correspondence. To expand the service to multiple devices, an interface buffer, the arbiter, is inserted between the processor and the devices. The arbiter will regulate the service request to the processor and then pass the granted service to a device one at a time.

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Priority Arbiter

A normal service request/grant protocol between a processor and a device is always on a one to one correspondence. To expand the service to multiple devices, an interface buffer, the arbiter, is inserted between the processor and the devices. The arbiter will regulate the service request to the processor and then pass the granted service to a device one at a time.

A specific application of a direct memory access (DMA) arbiter is shown in the figure. The "Hold Request" from each DMA controller (for example, an Intel 8257) 1 and 2 is sampled by a clock applied to the D-type flip-flops 3 and 4, respectively. Any valid request will generate a "Hold" signal to the processor 5 via NAND gate 6. When the acknowledge signal "HLDA" arrives from the processor 5 (for example, an Intel 8086), it will pass AND gate 7 and be latched in D-type flip-flop 8. Prioritizing is implemented with AND gates 9 and 10 by using higher priority latched request signals to block lower ones'. The highest priority latched request signal will then block off the sampling clock and send the latched "HLDA" to the corresponding DMA controller. Hence prioritizing is determined at the last moment when the processor grants its service. When the service request goes away, the sampling clock will resume for the next pending request level.

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