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Layout Scheme for FET LSI Structures

IP.com Disclosure Number: IPCOM000049269D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Cases, M: AUTHOR [+4]

Abstract

In digital computer structures, it is often necessary to implement a set of combinatorial logic structures where the inputs to each structure are randomly selected from a given set of binary variables. Field-effect transistor (FET) large-scale integrated (LSI) structures are described here that have optimum layout density, wirability, and engineering change (EC) flexibility.

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Layout Scheme for FET LSI Structures

In digital computer structures, it is often necessary to implement a set of combinatorial logic structures where the inputs to each structure are randomly selected from a given set of binary variables. Field-effect transistor (FET) large- scale integrated (LSI) structures are described here that have optimum layout density, wirability, and engineering change (EC) flexibility.

In these structures, the set of input signals is laid out in a bus configuration interlaced with the appropriate power buses. Then, the logical devices are individually formed underneath each selected input signal line and interconnected to form each logical output function. To illustrate, a set of two logical output functions with a set of nine (9) input signals is used as an example. f1=(A1+A2+A4+A5)B + C1C2

f2=(A1+A3)B + C3

The circuit representations using a depletion lead type technology are shown in Figs. 1a and 1b. Their physical layouts are shown in Fig. 2. For each output function, the logical devices are easily formed by placing thin recessed oxide (ROX) areas underneath the selected input polysilicon lines A1-C3, and properly interconnecting the source/drain regions of each device formed. The size of each logical device, as well as each load device, can be adjusted individually for optimum power performance operating point and beta ratio (Beta R) selection. Also, engineering changes are easier since the thin oxide (or ROX) area forming the logi...