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Logical Flexibility Enhancement for FET Logic Gates

IP.com Disclosure Number: IPCOM000049270D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Cases, M: AUTHOR [+3]

Abstract

In many system applications, it is desirable to obtain multi function logic capabilities from a single multi input combinatorial logic gate without drastically impacting the gate performance or layout density, thereby improving the overall system performance. Field-effect transistor (FET) logic structures provide a multi functional logical capability within a single gate with improved performance and density and have the added feature of individually tuneable power dissipation for each output load.

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Logical Flexibility Enhancement for FET Logic Gates

In many system applications, it is desirable to obtain multi function logic capabilities from a single multi input combinatorial logic gate without drastically impacting the gate performance or layout density, thereby improving the overall system performance. Field-effect transistor (FET) logic structures provide a multi functional logical capability within a single gate with improved performance and density and have the added feature of individually tuneable power dissipation for each output load.

The structures are organized according to the following technique. Given a set of desired logical functions sharing some common binary variables, the logical devices are ordered and interconnected appropriately (taking advantage of the built-in logical redundancy) to form the desired logical functions. Then load devices of the appropriate sizes are used at the desired outputs for optimum power performance operating points. This allows for multi functional implementations with single gate propagation delays.

As an example, consider a depletion type load technology and the following functions to be implemented: f1=(A+B)CD+E

f2=((A+B)CD+E)F+GH

By proper arrangement of the logic devices, the dual output AND OR Invert (AOI) logic circuit shown schematically in Fig. 1 is designed to implement the desired logic functions with a single gate propagation delay. The physical layout is shown in Fig. 2. The output load devices can...