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Bootstrapped Decoder Circuit for Low Supply Voltage Applications

IP.com Disclosure Number: IPCOM000049288D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Gabric, JA: AUTHOR

Abstract

This bootstrapped decode driver circuit includes a variable isolation device control voltage to enable the gates of output drivers to be precharged to the drain supply voltage while minimizing driver circuit area and parasitic capacitance. The driver includes a reference voltage generating circuit which includes a single depletion-mode device responsive to a non-critical timing pulse.

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Bootstrapped Decoder Circuit for Low Supply Voltage Applications

This bootstrapped decode driver circuit includes a variable isolation device control voltage to enable the gates of output drivers to be precharged to the drain supply voltage while minimizing driver circuit area and parasitic capacitance. The driver includes a reference voltage generating circuit which includes a single depletion-mode device responsive to a non-critical timing pulse.

The decoder circuit includes address (SAR) responsive input devices T1 and T2, precharge device T3, bootstrap isolation device T4, output driver T5 and clock pulse responsive depletion device T6. Device T6 and reference voltage VREF are common to a number of decoders and enable a boosted voltage to be generated on the gate of isolation device T4 in each decoder during the restore portion of each chip cycle. The VREF circuit also clamps the gates of isolation devices to supply potential V during a select cycle to prevent the isolation devices in selected decoders from becoming conductive during the bootstrapping of the gate of driver T5.

At the end of a previous restore cycle, node NA is precharged to V by T3 since restore pulse R is greater that V + Vt. Node NB is also precharged to V since VREF has been boosted to V + Vt during the restore of unselected decoders, as described below. Clock pulse CP is at ground, as are the inputs SAR and Vin. As the select cycle starts at time t1, R falls to ground and CP rises to V, thus discharging VREF through T6 to V. The...