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ROM Patching Mechanism Utilizing an Interrupt Facility

IP.com Disclosure Number: IPCOM000049313D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 4 page(s) / 63K

Publishing Venue

IBM

Related People

Perkins, CB: AUTHOR [+2]

Abstract

It is frequently necessary to alter programs, often in the field, that have been written in a read-only memory (ROM). The cost of effecting such changes can be significant, which has led to the use of a number of ROM patching mechanisms. One such arrangement 8 which is suitable for patching a ROM-based program 10 at any level, down to the instructions thereof, is shown in the above figure and described below.

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ROM Patching Mechanism Utilizing an Interrupt Facility

It is frequently necessary to alter programs, often in the field, that have been written in a read-only memory (ROM). The cost of effecting such changes can be significant, which has led to the use of a number of ROM patching mechanisms. One such arrangement 8 which is suitable for patching a ROM- based program 10 at any level, down to the instructions thereof, is shown in the above figure and described below.

In a common patch facility, it is normal to have a patch table and/or the actual patches loaded in RAM (random-access memory) as soon as possible after RESET/START. This requirement is also necessary in the presently described mechanism; that is, patches 12 and patch tables 14 are assumed to be stored in some form of alterable memory 18, such as RAM or alterable ROM. Also employed are a method of identifying an instruction to be patched and means for passing control to a patch facility. The method of patch identification utilizes a RAM 18 or other alterable memory that is N bits long, where N is the maximum number of possible patches. Each of the N bits is associated with one instruction, the instructions being assumed to be equivalent in length for descriptive purposes. The term "target" is used to refer to the instruction to be patched.

Upon target prefetch, the contents of the associated bit or patch identifier is gated to an interrupt controller 20. A logical zero (0) gated to the controller 20 will cause no action, while a logical one (1) will cause an interrupt and subsequent patch of the associated instruction. Thus, the presence of a 1 in the one-bit-wide RAM 18 indicates that its associated target is to be patched. When the interrupt is taken, control is passed to the interrupt/patch mechanism 22. Due to the assumption that instruction prefetch is being utilized, the interrupt will not take place and control is not passed until the current instruction executes. The interrupt/patch mechanism 22 may be implemented in hardware or microcode. The decision as to which implementation is selected will be based on each particular user's most significant constraint, that is, speed or low cost, respectively.

In either case, the interrupt/patch mechanism 22 must capture the NSIA (next sequential instruction address) and use that as a pointer into the patch address table 14. Table 14 will yield a new patched instruction address based on the old NSIA of the instruction to be patched. Control is then passed to the new instruction patch facility 12 which will, upon completion of the patched instruction, branch back to the instruction following the old patched instruction.

In most interruptible machines, the NSIA is automatically saved at interrupt time. The save area may be the machine stack, a context save area, a status register or other appropriate location. If this capability is not implemented in a particular machine, it will be necessary to capture the NSIA off the bus wh...