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High Speed Multiplier

IP.com Disclosure Number: IPCOM000049316D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Pivnichny, JR: AUTHOR

Abstract

This multiplier simultaneously processes the multiplicand and ier multiplier bits in pairs. Its operating speed is double or twice that of conventional arrays which process the bits individually.

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High Speed Multiplier

This multiplier simultaneously processes the multiplicand and ier multiplier bits in pairs. Its operating speed is double or twice that of conventional arrays which process the bits individually.

The multiplier is configured as a modified array 10 (Fig. 1). Recurring and identical partial product multipliers 11 (Fig. 2) and partial product adders 12 (Fig.
3) make it amenable to large-scale integration (LSI) and/or modular implementation. For sake of explanation, array 10 is shown as an eight-bit multiplier providing a sixteen-bit product R1-R16, where R1 and R16 are the least significant bit (LSB) 2/o/ and most significant bit (MSB) 2/15/, respectively.

Accordingly, sixteen multipliers 11 are arrayed in a four by four matrix. Each multiplier 11 provides a two-bit multiplication with a four-bit product. Terminals A and B are low- and high-order bit position input terminals, respectively, associated with the paired multiplicand bits. Terminals C and D are low- and high-order bit position input terminals, respectively, associated with the paired multiplier bits. The multiplicand bits P1-P8 are paired in ascending, successively higher order bits P1-P2, P3-P4, P5-P6, and P7-P8, bits P1 and P8 being the LSB 2/o/ and MSB 2/8/, respectively. Likewise, the multiplier bits Q1-Q8 are paired in ascending, successively higher order bits 01-Q2, Q3-Q4, Q5-Q6, and Q7-Q8, bits Q1 and Q8 being the LSB 2/o/ and MSB 2/8/, respectively. The four product bits of each multiplier 11 appear at its terminals E, F, G and H, respectively. Terminals E and H correspond to the low- and high-order bit positions, respectively, of the particular partial product.

In the first, i.e., top row of array 10, the low-order multiplier bit pair Q1-Q2 forms four partial products with the four multiplicand bit pairs P1-P2, P3-P4, etc., via the respective four multipliers 11 of the first row. The low-order bits Q1 and Q2 require no partial adders 12 in the first row. The product pair R1-R2 are formed directly with the low-order bit pairs Ql-Q2 and P1-P2 in the multiplier 11 located at the first row and first, i.e., right hand, column of array 10. A partial product adder 12 is associated with each multiplier 11 in each succeeding row.

The next higher order multiplicand bit pair Q3-Q4 forms four more partial products with the aforementioned multiplicand bit pairs P1-P2, etc., in the respective four multipliers 11 of the second row.

The for bits of the partial product appearing at the terminals E-H, respectively, of each multiplier 11 of the second and subsequent rows are fed to the input terminals J-M, respectively, of the particular adder 12 located in the same particular row and column as the particular multiplier 11. The two higher order bits of the partial product appearing at terminals G and H, respectively, of each multiplier 11 of the first row are fed to the terminals N and S, respectively, of the adder 12 located in the second row and same column...