Browse Prior Art Database

SCCA Compatibility Enhancement

IP.com Disclosure Number: IPCOM000049318D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Mitchell, MJ: AUTHOR

Abstract

U.S. Patent 4,155,117 describes a new multi-path synchronizing channel to channel adapter (SCCA). The protocol described therein significantly reduces the programming overhead of processor-to-processor communication. Referring to Fig. 1, it is seen that only one Start I/O (SIO) Instruction and one I/O Interruption per processor side are required to transfer a message. By using disconnected command chaining in conjunction with the SYNC commands, the path is committed and the data transfer commands. READ and WRITE, are entered only when both channel programs have been issued. Furthermore, each device address is available as a unique path, thus allowing up to 256 user/program assignable data links.

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SCCA Compatibility Enhancement

U.S. Patent 4,155,117 describes a new multi-path synchronizing channel to channel adapter (SCCA). The protocol described therein significantly reduces the programming overhead of processor-to-processor communication. Referring to Fig. 1, it is seen that only one Start I/O (SIO) Instruction and one I/O Interruption per processor side are required to transfer a message. By using disconnected command chaining in conjunction with the SYNC commands, the path is committed and the data transfer commands. READ and WRITE, are entered only when both channel programs have been issued. Furthermore, each device address is available as a unique path, thus allowing up to 256 user/program assignable data links.

Fig. 2 describes a typical processor to processor transaction with the current CTC (channel to channel) adapter in IBM System/360 (S/360) mode. The example assumes that CPU A is initiating a data transfer to CPU B. CPU A dispatches an SIO instruction. The channel program associated with this instruction contains a WRITE command. Several of the unused bits of the WRITE command byte may be encoded by the user/ program to convey predetermined information to the other side, such as the size of the data buffer storage area required to handle this transaction. Upon receipt of the WRITE command, the CTC adapter sends an ATTENTION asynchronous I/O interruption condition to the CPU B side. The ATTENTION acts as a "shoulder tap" event to the CPU B program. Next, the CPU B program issues an SIO instruction with a SENSE command in the channel program. This SENSE command fetches the WRITE command byte from the CTC adapter. The CPU B program can now interrogate the command byte including the encoded bits in order to determine what action is being requested. On the basis of this examination, CPU B constructs a channel program, which, in this example, is a READ data transfer command with the requested size data field specified. When CPU B issues the SIO instruction with this channel program, the READ command properly complements the pending WRITE command, and the data transfer takes place. The cycle completes on each side with an ending I/O interruption signaling completion of the data transfer.

Since the current CTC adapter hardware sequences as described above, existing programs are written according to these hardware conventions. In contrast, it has been shown that the SCCA significantly reduces the programming overhead of processor to processor communication, but at the expense of some amount of new programming support.

The subject of this article is an SCCA enhancement that will provide for easier migration of CTC users to the SCCA conc...