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Browse Prior Art Database

Integrated Vertical Channel JFET and Method of Manufacture

IP.com Disclosure Number: IPCOM000049331D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 111K

Publishing Venue

IBM

Related People

Anantha, NG: AUTHOR [+3]

Abstract

NPN transistors are incorporated into a semiconductor by means of a self-aligned process which permits the density of the devices to be increased in the substrate. The JFET (junction field-effect transistor) may be adapted to serve as a high resistance load device for a bipolar circuit incorporating the transistors.

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Integrated Vertical Channel JFET and Method of Manufacture

NPN transistors are incorporated into a semiconductor by means of a self- aligned process which permits the density of the devices to be increased in the substrate. The JFET (junction field-effect transistor) may be adapted to serve as a high resistance load device for a bipolar circuit incorporating the transistors.

In Fig. 1, a P+ poly mask 10 is formed on an N+ substrate I2 and N epitaxial layer 14 by the following steps: A. CVD (chemically vapor deposit) 3,000 angstroms intrinsic

polysilic 10.

B. CVD 500 angstroms screen oxide (not shown).

C. Ion implant polysilicon 10 (boron, 5 x 10/15/ cm/2/, 50

KeV).

D. Apply photoresist (not shown) for the poly mask.

E. Reactive ion etch an opening in 500 angstroms screen oxide.

F. Strip photoresist (not shown).

G. Reactive ion etch 3,000 angstroms polysilicon 20 with oxide

mask. Dip etch the polysilicon residue, if needed.

In Fig. 2, a reach-through implant is formed by the following steps:

A. Grow 300 angstroms thermal screen oxide 16.

B. Apply photoresist (not shown).

C. Ion implant reach-through 18 with phosphorus in deep

end shallow doses.

D. Strip photoresist (not shown).

In Fig. 3, the emitter of a bipolar transistor and a source of a JFET transistor are formed by the following steps: A. CVD 4,000 angstroms of a screen oxide 20 to obtain at least

3,000 of oxide over the JFET area.

B. Apply a photoresist (not shown) to form a mask which will

open the emitter of an NPN transistor and the source of a

JFET.

C. Reactive ion etch 4,000 angstroms of a screen oxide 18 and

20.

In Fig. 4, a block-out mask is formed such that the emitter of the NPN transistor is open while the source of the JFET is blocked out by the following steps: A. Reactive ion etch 3,000 angstroms of polysilicon with the

oxide mask and dip etch the remaining polysilicon residue

if needed.

B. Grow 300 angstro...