Browse Prior Art Database

ESD Protection Without Parasitic NPN

IP.com Disclosure Number: IPCOM000049347D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Knepper, LE: AUTHOR

Abstract

An arrangement is described to provide electrostatic discharge (ESD) protection to chip I/O terminals without the parasitic NPN transistor action which accompanies conventional ESD protection schemes.

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ESD Protection Without Parasitic NPN

An arrangement is described to provide electrostatic discharge (ESD) protection to chip I/O terminals without the parasitic NPN transistor action which accompanies conventional ESD protection schemes.

Fig. 1A shows a conventional ESD protection device, along with its associated parasitic NPN transistor 1 (shown by the dashed transistor symbol). The emitter-base junction of transistor 1 is formed by N(+) region 3 and P substrate region 5, while the collector-base junction of this transistor is formed by N(+) region 7 and P substrate region 5. In the schematic representation shown in Fig. 1B, ESD protect diode 9 corresponds to the emitter-base junction of transistor 1.

Fig. 2A shows an arrangement for ESD protection without a parasitic NPN transistor. As can be seen, SBD (Schottky barrier diode) contact 11 is made to the arrangement via N/-/ region 13, with the SBD being in series with the diode formed by N/+/ region 3' and P/-/ substrate region 5', the latter being grounded analogously to that described in Fig. 1. A schematic representation of the diode configuration is shown in Fig. 2B. In this arrangement, one of the diodes will be on while the other breaks down for any ESD polarity. However, for smaller operating voltages, such as negative overshoots, one diode will always be reverse-biased and no parasitic conduction (or NPN) results. The scheme requires the same chip area as shown in Fig. 1 but results in less parasitic ca...