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Static/ Dynamic Fault Relocation for a Fault Tolerant Memory

IP.com Disclosure Number: IPCOM000049349D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Bosch, LJ: AUTHOR [+3]

Abstract

By selectively transforming addresses from a memory fault location to an off-chip spare location an error free operation can be achieved for a broad spectrum of partially defective array chips/ locations. The off-chip chip location, for the spare as well as for the address translation logic, is advantageous in that the memory chips can be packaged without regard to the location of the faulty bits. The locations can be ascertained at card test time, and the external translation logic can be programmed accordingly. This transformation can be performed at any level of assembly (card through system) where the array geometry is fixed (modules mounted) and access to the address translation logic is available.

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Static/ Dynamic Fault Relocation for a Fault Tolerant Memory

By selectively transforming addresses from a memory fault location to an off-chip spare location an error free operation can be achieved for a broad spectrum of partially defective array chips/ locations. The off-chip chip location, for the spare as well as for the address translation logic, is advantageous in that the memory chips can be packaged without regard to the location of the faulty bits. The locations can be ascertained at card test time, and the external translation logic can be programmed accordingly. This transformation can be performed at any level of assembly (card through system) where the array geometry is fixed (modules mounted) and access to the address translation logic is available.

For static fault relocation, the address translation logic is personalized once and remains "fixed" (PROM, PLA, for example). For dynamic fault relocation, the address translation logic can be altered whenever a "new" set of fault conditions appear (i.e., at card test, system test, or field operation) through the use of alterable logic (EPPROM (Erasable Programmable Read-Only Memory), FPLA (Field Programmable Logic Array), Associate Memory are examples).

The bit fault locations may be a line, contiguous lines, randomly scattered lines, or segments. Furthermore, these faults may be in the word dimension, in the bit dimension, or in both dimensions.

The figure shows a matrix of arrays arranged in Columns 1...