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Consecutive Error Correction

IP.com Disclosure Number: IPCOM000049350D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Aichelmann, FJ: AUTHOR

Abstract

This is a technique that extends the capability of error checking and correction logic by storing away correctable word locators for subsequent correction of additional errors.

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Consecutive Error Correction

This is a technique that extends the capability of error checking and correction logic by storing away correctable word locators for subsequent correction of additional errors.

In memory systems error checking and correction (ECC) logic is used to minimize the effects of errors and improve product reliability. Fig. 1 depicts a typical memory system comprised of multiple memory array units 1-N and a storage subsystem 3 which includes an ECC facility 4. Fig. 2 shows a conventional structure of an ECC facility for read operations. The syndromes S(j) (resulting from the comparison of the generated check bits G(j) with the stored check bits C(j)) are used, when correctable errors occur, to identify the defective locations (5) so that correction (6) can be made. In conventional coding, an odd number of active syndromes denotes (7) correctable error. An even number of active syndromes indicates (8) uncorrectable errors.

The present technique of Fig. 3 increases the correctability of uncorrectable errors without using multiple memory array accesses to enhance ECC correctability. This is accomplished by storing away (9) the syndromes of correctable locations so that when that memory word becomes uncorrectable upon the occurrence of an additional error, the stored syndromes can be recalled from an array (correctable bit location storage 9) so that in effect the first failure can be erased with the correction feedback (10) passing through the ch...