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Schottky Current Switch Circuit Configuration Capable of Driving High Capacitive Loads

IP.com Disclosure Number: IPCOM000049352D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Abilevitz, B: AUTHOR [+4]

Abstract

The article describes the concept of achieving performance improvement on an SCS (Schottky Current Switch) masterslice layout by transferring the wiring capacitance of long interconnections from collector outputs to emitter follower outputs. When a high capacitance net is identified, an on-chip driver (which can be regarded as a part of a standard SCS gate) is substituted for the driving gate and an on-chip receiver placed near the receiving gate acts as a buffer for the signal.

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Schottky Current Switch Circuit Configuration Capable of Driving High Capacitive Loads

The article describes the concept of achieving performance improvement on an SCS (Schottky Current Switch) masterslice layout by transferring the wiring capacitance of long interconnections from collector outputs to emitter follower outputs. When a high capacitance net is identified, an on-chip driver (which can be regarded as a part of a standard SCS gate) is substituted for the driving gate and an on-chip receiver placed near the receiving gate acts as a buffer for the signal.

Standard SCS gates have an in-phase and an out-of-phase output, and the outputs are collector driven. The (metal) interconnection line connecting the output of one SCS gate, i.e., gate A in Fig. 1, to the input of another gate, i.e., gate B, has a certain capacitance associated with it. This capacitance is designated CL in Fig. 1. Capacitance CL hanging on the output collector results in an R-C time constant which can significantly degrade the performance of the circuit. When one circuit drives another circuit at an opposite end of the chip, the capacitance CL may become intolerably large. This holds particularly true following the trend towards larger and larger chip sizes.

The proposed solution to the capacitive loading problem is to transfer CL from the collector to the emitters, as shown in Fig. 2. This change in loading is physically accomplished by using as a reference device an on-chip receiver c...