Browse Prior Art Database

Split Phase Memory Driver

IP.com Disclosure Number: IPCOM000049353D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Gaudenzi, GJ: AUTHOR [+3]

Abstract

The driver circuit illustrated in the drawing allows bipolar logic circuits to interface to FET memories which require positive logic levels in excess of +2.8 V at 220 MuA DC and limited down-going output transitions such that negative overshoots do not exceed -1.0 V. This driver circuit meets these requirements as described below.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Split Phase Memory Driver

The driver circuit illustrated in the drawing allows bipolar logic circuits to interface to FET memories which require positive logic levels in excess of +2.8 V at 220 MuA DC and limited down-going output transitions such that negative overshoots do not exceed -1.0 V. This driver circuit meets these requirements as described below.

Transistors T3 and T4 form a push-pull network such that the driver can drive high capacitive loads. Transistor T3 establishes the up level for this circuit at approximately VC-Vbe, about 3.2 V at 220 MuA at the output A. Diodes D1 and D2 act as clamps such that the output level does not exceed +3.7 V when the power supply is high, and provides some performance enhancement when the output is pulling down. The split-phase input circuitry of T1 and T2 ensures that T3 does not conduct when the output is below 0.3 V, since the base of T3 is clamped at about 0.8V when the output is down.

Negative overshoots are limited to about -1.0V by controlling Delta v/Delta t via the feedback capacitor (.5 pF) and the series damping resistor of 40 ohms (Rp). Rvv is a clamp resistor which establishes the most positive up level (MPUL) of +3.7 V by ensuring that transistor T3 always conducts a standby current (about 100 microamps).

1

Page 2 of 2

2

[This page contains 3 pictures or other non-text objects]