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Memory Driver with Split Damping Resistor

IP.com Disclosure Number: IPCOM000049354D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Gaudenzi, GJ: AUTHOR [+3]

Abstract

The driver circuit illustrated in Fig. 1 is implemented in bipolar logic technology to interface to FET memories which require positive logic levels in excess of +2.8 V at 220 microamps DC and limited down going output transitions such that negative overshoots do not exceed 1.0 V. This driver circuit meets these requirements as described below.

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Memory Driver with Split Damping Resistor

The driver circuit illustrated in Fig. 1 is implemented in bipolar logic technology to interface to FET memories which require positive logic levels in excess of +2.8 V at 220 microamps DC and limited down going output transitions such that negative overshoots do not exceed 1.0 V. This driver circuit meets these requirements as described below.

Transistors T2 and T3 form a push-pull network capable of delivering current limited by R1 for up-going transitions and R2 for down-going transitions. T1 acts as a phase splitter which switches T2 and T3 on and off alternately. The classical totem-pole diode has been eliminated to raise the least positive up level (LPUL) to about +3.2 V at 220 MuA. The R1 damping resistor limits the peak current for upgoing transitions such that load ringing is reduced under all conditions. The R2 resistor limits the current which can be pulled off the line, reducing the ringing on the external net and ensures that the output voltage does not exceed -1.0 V. The combination of (R1+R2) limits the current that can flow out of T2 when T3 is on, due to the clamp diode on, allowing some conduction in T2 when the output is down. This condition adds about 3 mw power dissipation to the driver, but provides enhanced delays.

A modification of this circuit, shown in Fig. 2, is used when transistor Tl does not have a SBD (Schottky barrier diode) clamp between the base and collector. Under these conditions T2 do...