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Push Pull FET Driver without Phase Splitter

IP.com Disclosure Number: IPCOM000049355D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Gaundenzi, GJ: AUTHOR [+3]

Abstract

This circuit accepts input logic levels in the range 0 V to 0.9 V from internal circuits, and provides output logic levels of greater than 3 V at 300 MuA and less than 0.5 V at 300 MuA for driving FET loads on other chips.

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Push Pull FET Driver without Phase Splitter

This circuit accepts input logic levels in the range 0 V to 0.9 V from internal circuits, and provides output logic levels of greater than 3 V at 300 MuA and less than 0.5 V at 300 MuA for driving FET loads on other chips.

The operation of the circuit is as follows: When the input A is high, T2 conducts, ensuring that the output A is at a logical down level. The diode D1 clamps the base of transistor Tl such that the voltage across resistor R2 is sufficient to hold T1 in essentially a non-conducting state. The power in this condition is minimized by selecting a large value of Rl without degrading the performance.

When the input A is low, transistor T2 turns off, allowing its collector voltage to rise and shutting off diode D1. The current flowing through resistor R1 is therefore diverted into the base of transistor T1, allowing it to function as a conventional emitter follower and charge the load to a final value of Vcc-Vbe.

The resistor RZ is selected to match the output impedance of the driver to the characteristic impedance of the load in order to minimize electrical reflections.

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