Browse Prior Art Database

Improves Decoding Timing for One Device FET Random Access Memory Arrays

IP.com Disclosure Number: IPCOM000049357D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Lo, TC: AUTHOR [+3]

Abstract

This is a technique for delaying column decoding in field-effect transistor (FET) random-access memory (RAM) arrays until critical sensing has been completed. In this way, substrate noise generated by column decoding is prevented from disturbing the sensing operation.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Improves Decoding Timing for One Device FET Random Access Memory Arrays

This is a technique for delaying column decoding in field-effect transistor (FET) random-access memory (RAM) arrays until critical sensing has been completed. In this way, substrate noise generated by column decoding is prevented from disturbing the sensing operation.

As shown in the figure, a memory cell 10 is first accessed by means of row decoder 12. The word line (WL) accesses an entire row of cells. One device cells are known to include one FET and a capacitor, with the WL connected to the gate electrode of each of the FETs in a row. The cell output is usually taken along the bit line (BL). The BL is usually a source or drain of the FET. A sense circuit 14 is connected to each BL.

Previously, column decoding in column decoder 16 sometimes occurred at the same time as sensing in circuit 14 (known as first sensing). The timing of the first sensing operation is determined by the discharging of the common source sense line (SL) initiated by the latch timing generator 22. Prior to the present technique, column decoder 16 was responsive to an undelayed column enable clock signal.

The column decoding operation in column decoder 16 occurs in response to the column enable clock and causes noise signals in the substrate which are then coupled non-symmetrically into the bit lines (BL & BL). The timing and amplitude of the noise signals vary among the bit lines. This is of particular concern in differential sensing techniques where a pair of bit lines BL and BL, inputting a differential signal into a sense circuit 14, receive different amplitudes of noise. Noise amplitudes are even more critical in memory chips having an on- chip substrate bias voltage generator, which cannot hold a substrate to the same le...