Browse Prior Art Database

Testing Mixed Storage and Logic Chips

IP.com Disclosure Number: IPCOM000049376D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Gepraegs, HW: AUTHOR [+2]

Abstract

Fig. 1 shows chip 1 with a logic and a storage section. Part of the logic section functions independently of the storage section. The arrangement described permits independent testing of the logic and storage sections. For this purpose, special test wiring is provided on the chip, using the topmost layer to realize the test connections with small contact areas (pads) 3. Signals are applied to and received from areas 3 by needles being pressed against them. The input and output connections of the chip are realized as usual by contact areas 2 and balls 4. Figs. 2 and 3 show the physical arrangement of the contact areas and balls, Fig. 3 showing the cross-section A-A according to Fig. 2. The small areas 3 are realized on an otherwise unused silicon surface.

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Testing Mixed Storage and Logic Chips

Fig. 1 shows chip 1 with a logic and a storage section. Part of the logic section functions independently of the storage section. The arrangement described permits independent testing of the logic and storage sections. For this purpose, special test wiring is provided on the chip, using the topmost layer to realize the test connections with small contact areas (pads) 3. Signals are applied to and received from areas 3 by needles being pressed against them. The input and output connections of the chip are realized as usual by contact areas 2 and balls 4. Figs. 2 and 3 show the physical arrangement of the contact areas and balls, Fig. 3 showing the cross-section A-A according to Fig. 2. The small areas 3 are realized on an otherwise unused silicon surface.

For testing the logic input part of the chip, input signals are applied to connections 2A. The resulting output signals are received at connections 3B or 2B. A logic test (LT) signal is applied to connection 3A, disabling the storage section.

For testing the storage section, connections 3B are used as inputs. Output signals from the storage section are received at connections 3C. A control or storage test (ST) signal is applied to the chip, disabling the part of the logic section connected to the storage.

For testing the output logic section of the chip, test signals are applied to connections 3C, with output signals being received at connections 2B.

The chip is tested during...