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Instruction Buffer Addressing

IP.com Disclosure Number: IPCOM000049383D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Getzlaff, KJ: AUTHOR [+4]

Abstract

An address generation circuit with reduced address register capacity is described for an instruction buffer whose two halves are simultaneously read out and refilled, respectively.

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Instruction Buffer Addressing

An address generation circuit with reduced address register capacity is described for an instruction buffer whose two halves are simultaneously read out and refilled, respectively.

For time-overlapped operation of an instruction buffer 1 (Fig. 1) two address registers 2, 4 are required, a load register 4 for refilling the buffer and a read register 2 for reading out the instruction to be processed; the latter address represents the current address IAR of the processor, and is required for interrupt processing and other system uses.

To reduce address register circuits it is proposed to restrict the capacity of read register 2 to the address range of the buffer instead of providing for the whole system address. An incrementer 3 for consecutive addressing of the buffer contents is thus also reduced to the smaller bit capacity. Load register 4 is used to access the system store 5 and has, of course, to provide for all system address bits 8 to 31.

To calculate the current system address IAR from the reduced load register 2 it is, however, necessary to provide for more address bits in the load register (in the example additional address bit 28) than would be required for addressing the small buffer capacity. If the buffer capacity corresponds to eight bytes as in Fig. 2, the first four bytes of a block n with address bit 28 = 0 are read at time t(1) when the last four bytes of the same block n are transferred to the second half of the buff...