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Address Error Detection for Memory Using SEC/DED with Processor Using Byte Parity Error Detection

IP.com Disclosure Number: IPCOM000049390D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Kaufman, DR: AUTHOR

Abstract

In a data processing system in which memory addresses and other data are protected from a single error by a byte parity bit, the parity bits of the address are applied to the SEC/DED (single error correction/ double error detection) check bit generator of the memory along with the bits of a word that are to be stored in the memory. The parity bits themselves are not stored. When the word is fetched from memory, the parity bits of the address are similarly applied to the syndrome bit generator. A single error in any byte of the address is detected.

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Address Error Detection for Memory Using SEC/DED with Processor Using Byte Parity Error Detection

In a data processing system in which memory addresses and other data are protected from a single error by a byte parity bit, the parity bits of the address are applied to the SEC/DED (single error correction/ double error detection) check bit generator of the memory along with the bits of a word that are to be stored in the memory. The parity bits themselves are not stored. When the word is fetched from memory, the parity bits of the address are similarly applied to the syndrome bit generator. A single error in any byte of the address is detected.

Memory words are commonly protected by check bits that are stored with the memory word and provide SEC/DED for errors that are caused by a failure in the memory or the associated circuits. Other components of the central processor commonly operate with a byte parity check bit. The memory usually includes circuits for making a parity check on each byte of data and address that is supplied to the memory. However, it is possible for an address error to occur in the address decoder circuits or in other circuits that operate on the address after the parity check. There have been many proposals for attaching address check bits to each memory word. The technique of this article takes advantage of the fact that most SEC/DED systems do not use the full capacity of the error correction code. For example, a 32-bit memory word requires...