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04-82 p6139-6147. Channel Set Switching Mechanism

IP.com Disclosure Number: IPCOM000049402D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 4 page(s) / 51K

Publishing Venue

IBM

Related People

Wansor, DH: AUTHOR [+4]

Abstract

In a data processing system containing central and I/O processing subsystems which share access to a common main storage subsystem, in which the central processing system comprises at least two central processing units (CPUs) and the I/O processing subsystem comprises a processor which supervises the traffic through multiple I/O channel interfaces between the CPUs and I/O control units and devices, it is desirable to be able to associate the channel interfaces with the CPUs in various configurations. It is also desirable to be able to do this dynamically while central processing and I/O operations are being conducted. This capability can be used, for instance, to enable the central processing system to recover from a failure of one or more CPUs by associating channels of the failed CPU with another CPU.

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04-82 p6139-6147. Channel Set Switching Mechanism

In a data processing system containing central and I/O processing subsystems which share access to a common main storage subsystem, in which the central processing system comprises at least two central processing units (CPUs) and the I/O processing subsystem comprises a processor which supervises the traffic through multiple I/O channel interfaces between the CPUs and I/O control units and devices, it is desirable to be able to associate the channel interfaces with the CPUs in various configurations. It is also desirable to be able to do this dynamically while central processing and I/O operations are being conducted. This capability can be used, for instance, to enable the central processing system to recover from a failure of one or more CPUs by associating channels of the failed CPU with another CPU.

Fig. 1 shows a central system of this type including two CPUs, denoted CPU(a) and CPU(b), at least one I/O processing unit (IOPU) governing operations of plural I/0 channels (a system may have more than one such unit), a main store, and a common storage controller facility (SC) which interfaces between the storage and the CPUs and IOPUs. For providing the desired capability of switching channel sets, the main store subsystem may be divided into two disjoint parts: a "common area" part (not shown) accessible to all programs including user (i.e., "problem") programs, and a "system area" part reserved for configuring functions including channel set assignment.

The system area includes four disjoint parts for channel set assignment as follows: a part 1.1 associated with a subset m of the total of n channels supervised by the IOPU, a part 1.2 associated with the remaining n-m of the n channels, a part 1.3 associated with CPU(a), and a part 1.4 associated with CPU(b).

The m channel subset part 1.1 contains a word presently called "Channel Set m Control" byte which denotes the configuration and CPU association of the respective channel subset. This control byte contains bits having specific control functions as follows: A bit called "Channel Set m Operational" which denotes whether or not the entire subset of m channels is configured for operation. A bit called "Channel Set m Connected" which denotes connection of the entire subset of m channels to a particular CPU for acceptance of I/O initiative, indication of I/O interruption requests, and transfer of interruption status. A bit called "Odd Channel Set" which identifies uniquely the entire subset of m channels relative to the remaining subset of n-m channels. A bit called "2 IOPUs Installed" distinguishing a system containing two IOPUs from a system containing only one IOPU. A bit called "Odd IOPU" which directs flow from the respective CPU to one IOPU relative to the subset of m channels (in a system containing two IOPUs). A field called "Connected Central Processing Unit Address" which identifies the CPU currently associated with the s...