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Browse Prior Art Database

Multi-Chip Power Hybrid Module

IP.com Disclosure Number: IPCOM000049428D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Wright, WL: AUTHOR

Abstract

This design concept provides reduced thermal resistance paths between power dissipating elements of a VLSI (very large-scale integration) function and a heat sink, with a substrate wireability and module I/O capability to support the circuit requirements of that function. By using a combination of packaging features, this design also achieves high utilization of substrate surface area for component mounting, and a versatile I/O termination technique that does not significantly impact substrate design. Assembly costs of this module design are minimized through the use of premolded components and low-cost joining processes.

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Multi-Chip Power Hybrid Module

This design concept provides reduced thermal resistance paths between power dissipating elements of a VLSI (very large-scale integration) function and a heat sink, with a substrate wireability and module I/O capability to support the circuit requirements of that function. By using a combination of packaging features, this design also achieves high utilization of substrate surface area for component mounting, and a versatile I/O termination technique that does not significantly impact substrate design. Assembly costs of this module design are minimized through the use of premolded components and low-cost joining processes. Module testability and reworkability is enhanced by the ability to functionally test the populated ceramic substrate through its perimeter pads prior to attachment to the copper base or through the I/O pins prior to cap attachment.

The design concept provides a meens of enhancing chip power dissipation capacity of multi-chip modules while using the substrate technologies developed to achieve enhanced wireability.

A cross-section of the power hybrid design is shown in Fig. 1. The construction consists of a thin (approximately 25 mils thick) ceramic substrate10, 10, attached to a copper base 12 with thermally conductive epoxy 14. The substrate can be a single level metal (thick film or metallized ceramic or multilevel metal depending on substrate circuit requirements. Connections to the I/O pins are made by means of...