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Electrically Alterable Read-Only Memory Array

IP.com Disclosure Number: IPCOM000049457D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Chao, HH: AUTHOR

Abstract

The fabrication of this electrically alterable read-only memory (EAROM) is compatible with the standard MOSFET technology which is designed for the memory and/or logic.

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Electrically Alterable Read-Only Memory Array

The fabrication of this electrically alterable read-only memory (EAROM) is compatible with the standard MOSFET technology which is designed for the memory and/or logic.

An EAROM array using floating gate FETs in the cells is proposed in this article. The equivalent circuit of the device is shown in the figure. Clearing the memory is accomplished by erasing every device in a block. This is done by grounding all bit lines and program lines while taking the erase line to a very high voltage to attract electron flow out of the floating gates through the dual electron injector structure (DEIS) as described in (1). Programming is accomplished by writing selected bits within a word. The erase line and word lines are held at ground. The program line is biased to a high positive voltage V(p) to raise the potential of the floating gate through capacitance C(3). The device is designed such that the voltage across the DEIS is still less than the threshold voltage of the DEIS. Thus, electrons do not flow into the floating gates.

However, the voltage across the DEIS provides an offset to the threshold voltage of the DEIS and lowers the required program voltage on the bit line during the program operation. The selected bit lines are then charged up to V(pp) (program voltage on the selected bit lines). Since the channel of the floating gate FETs on the selected program line is turned on, voltage V(pp) is coupled into the floating gates of the selected cells via the channel capacitance C(1). Thus, electrons flow into the floating gates.

The voltage limitation of V(pp) is the gate bound junction breakdown voltage at ground gate bias. In order to keep V(pp) within the limitation of the technology, the voltage coupling coefficient from the bit line to the floating gate has to be greater than 0.5. To achieve this, C has to be larger than C(2) +C(3), which conflicts with the requirement of having a large voltage coupling coefficient from the program line to the floating gate which needs large C(3). However, since decoding is not required for the common program line, it can be driven by an off- chip driver or by special on-chip high voltage circuits, which are not feasible for driving the line which requires decoding due to their large pitch and area. Thus, the...