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Cache Splitting with Information of XI Sensitivity in Tightly Coupled Multiprocessing Systems

IP.com Disclosure Number: IPCOM000049462D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Liu, L: AUTHOR

Abstract

In multiprocessing systems the Cross Interrogate (XI) phenomenon results when shared data are used relatively closely together by different CPUs. The performance penalties incurred by XIs are expected to be high when the number of CPUs grows. It is known that certain data areas in some software systems (e.g., MVS and IMS) cause a large portion of the XIs. In order to reduce the ping ponging of XI-sensitive data among the CPUs, it may be desirable to use smaller caches dedicated to the references of such sensitive data.

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Cache Splitting with Information of XI Sensitivity in Tightly Coupled Multiprocessing Systems

In multiprocessing systems the Cross Interrogate (XI) phenomenon results when shared data are used relatively closely together by different CPUs. The performance penalties incurred by XIs are expected to be high when the number of CPUs grows. It is known that certain data areas in some software systems (e.g., MVS and IMS) cause a large portion of the XIs. In order to reduce the ping ponging of XI-sensitive data among the CPUs, it may be desirable to use smaller caches dedicated to the references of such sensitive data.

As shown in the figure, consider a cache splitting scheme as follows: Two local caches, named Cache 1 and Cache 2, are associated with each CPU. Certain data areas of the system software are preclassified as XI-sensitive. Cache 1 (cache 2, resp.) is dedicated to the references of XI-sensitive (non XI sensitive, resp.) data. It is usually desirable to make the size of Cache 1's small in order to achieve a fast replacement effect. Upon a reference the two local caches are searched in parallel (with, at most, one possible hit in, at most, one of the local caches). Upon a local miss (of both local caches) the system (say, the SCU (System Control Unit)) will determine whether the data referenced is XI- sensitive or not, and hence will decide which of the local caches is the receiver of the newly fetched line. If the reference is a D-fetch (i.e., a data fetch) a...