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Non-Complementary MOS Domino Logic Circuit

IP.com Disclosure Number: IPCOM000049469D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Terman, LM: AUTHOR

Abstract

This article relates generally to MOS logic circuits and more specifically to MOS logic circuits which are characterized as domino logic circuits. These circuits are so-called because, under appropriate conditions, a logic front propagates from the first stage of a logic circuit through successive stages by the conditional discharging of successive circuit nodes in a glitch-free manner. A circuit of this character in complementary MOS technology has been described in 1981 ISSCC Digest of Technical Papers in an article entitled A CMOS 32b Single Chip Microprocessor by Murphy, et al, pp. 230-231. The circuit described has no standby power and dissipates power only when the circuits are switching.

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Non-Complementary MOS Domino Logic Circuit

This article relates generally to MOS logic circuits and more specifically to MOS logic circuits which are characterized as domino logic circuits. These circuits are so-called because, under appropriate conditions, a logic front propagates from the first stage of a logic circuit through successive stages by the conditional discharging of successive circuit nodes in a glitch-free manner. A circuit of this character in complementary MOS technology has been described in 1981 ISSCC Digest of Technical Papers in an article entitled A CMOS 32b Single Chip Microprocessor by Murphy, et al, pp. 230-231. The circuit described has no standby power and dissipates power only when the circuits are switching.

The present article shows a pair of such circuits in non-complementary MOS technology which accomplish a similar result. Fig. 1 shows a three-input NOR circuit. When phi is high, node A discharges to ground and node B is pulled high as a result of the turning on of device TL2 and the turning off of device TD. There is no standby power dissipated, since the load device TL1 is turned off, as is device TD. In a block of logic made up of a chain of circuits similar to the circuit of Fig. 1, all nodes A are low and all output nodes B are high for all the circuits.

When phi goes low, instantaneously all nodes A remain low and all nodes B remain high since the logic inputs A, B, and C are provided by nodes B of preceding circuits, causin...