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Logic Processor for Logic Simulation Machine

IP.com Disclosure Number: IPCOM000049473D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 4 page(s) / 75K

Publishing Venue

IBM

Related People

Denneau, M: AUTHOR

Abstract

The following is a summary of the architectural innovations of a logic simulator. 1. Rank Order Simulation Capability

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Logic Processor for Logic Simulation Machine

The following is a summary of the architectural innovations of a logic simulator. 1. Rank Order Simulation Capability

The original Logic Simulation Machine, which will be referred to here as LSM- I, was designed solely for unit delay simulation. During any particular execution of the instruction sequence (1024 instructions for a full machine), gate inputs are fetched from the A data and switch memories, while gate outputs along with data provided by the switch are stored in the B data and switch memories. At the end of the sequence, the roles of A and B are reversed. As a result of this organization, the simulated propagation of logic signals occurs at a rate of ONE GATE DELAY for each execution of the ENTIRE instruction sequence. Since IBM machines are typically constructed from synchronously clocked latches separated by an average of ten to twenty levels of purely combinational logic, the Logic Simulation Machine will require TEN TO TWENTY PASSES through its instruction sequence in order to simulate the propagation of a set of signals from an input latch to an output latch.

With the organization of the described Logic Simulation Machine in Figs. 1 and 1A, however, we can accomplish the same propagation with ONLY ONE PASS through an instruction sequence. Define a gate to be of rank 1 if all of its inputs come from the input latch. Define a gate to be of rank 2 if it is not of rank 1 and if all of its inputs come from the input latch or from gates of rank 1. Proceeding in this manner, define a gate to be of rank N+1 if it is not of rank N and if all of its inputs come from the input latch or from gates of rank N or less. Since data in the Logic Simulation Machine can be fetched from any location in the switch and local data memories and since the result of a gate computation can be stored back into any location in the local data memory, the output of the network can be obtained as follows. First, compute the outputs of all gates of rank 1. Next, using the values just obtained, compute the outputs of all gates of rank 2. Continue in this manner until all gate outputs have been computed. Thus, computing each gate output ONLY ONCE, the output of the combinational network is obtained.

This rank order simulation capability will also provide corresponding performance improvements in test generation applications where many patterns are propagated between LSSD (level sensitive scan design) latches through combinational logic. 2. Reduction of Data Storage

The A/B organization of LSM-I requires that the number of three bit words (two data plus one parity) reserved for data storage be sixteen times the number of gates to be simulated (four copies each of A/B, switch/logic data). This entails substantial cost, since the data storage will typically be implemented with expensive high speed random-access memory chips.

Rank-order simulation, on the other hand, has an amount of data storage equal to onl...