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Interruption Scheme for Vector Instructions

IP.com Disclosure Number: IPCOM000049482D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Liles, AG: AUTHOR [+2]

Abstract

This article describes a technique for saving the status of a vector instruction when interrupted so that the instruction may be resumed later. Interrupt and Vector Instructions

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Interruption Scheme for Vector Instructions

This article describes a technique for saving the status of a vector instruction when interrupted so that the instruction may be resumed later. Interrupt and Vector Instructions

Register-to-register operations on logical vectors within the vector ring may involve many elements and, consequently, take many cycles to complete. During this time period an interrupt may occur. The question to be addressed is whether to let the instruction complete or to interrupt the vector instruction and preserve the status for later restart.

In addition to the asynchronous interrupts, the LOAD and STORE vector instructions can generate page fault interrupts. These page faults can, of course, be eliminated by page fixing as is done with I/O (input/output) equipment, but a price is paid in the overhead generated by the page fix along with the potential degradation of unavailable pages resulting from unnecessary page fixing.

In any case, the machine environment (hardware or software) external to the vector register ring may necessitate responding to the interrupt prior to the completion of the vector instruction. The following areas are addressed: 1. How and where to interrupt vector instructions.

2. How to restart interrupted vectors.

3. Effect of interrupts on chaining and overlap.

Interrupting and Restarting Vector Instructions

A logical vector is defined by a beginning, end, orientation, and mask. The vector ring elements corresponding to "1" bits in the mask ring participate in the vector instruction. A hardware pointer exists that keeps track of the current element of the logical vector participating in the vector instruction. This pointer will be referred to as the current operand pointer (COP).

At the beginning of the operation, the COP points to the physical vector origin. As the operation proceeds, the COP will point to the next mask bit to start the search for a participating element. Conceptually, the COP is updated continually as each bit of the mask vector is checked for a "1" state. When the operation is complete, an End of Operation Symbol (EOS) is placed in the COP. This EOS does not correspond to any possible vector ring address, and thus can be recognized by the hardware as an instruction complete indication. The C0P is initialized and modified as follows:

(1) The "set physical vector origin" instruction also sets

the origin value into the COP.

(2) When the instruction starts execution, the COP is

checked to s...