Browse Prior Art Database

Sequential I-Fetching Mechanisms

IP.com Disclosure Number: IPCOM000049483D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Pomerene, JH: AUTHOR [+3]

Abstract

Simulation studies of performance of highly pipelined single cache bus processors show that the empty I-Buffer increases with the STORE PA (putaway) cycles. A design with a two-cycle store putaway has considerably more empty I-Buffer than a design with a single-cycle putaway. More detailed studies highlight that the empty I-Buffer is caused by sequential I-Fetching which has not been done on a timely basis.

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Sequential I-Fetching Mechanisms

Simulation studies of performance of highly pipelined single cache bus processors show that the empty I-Buffer increases with the STORE PA (putaway) cycles. A design with a two-cycle store putaway has considerably more empty I- Buffer than a design with a single-cycle putaway. More detailed studies highlight that the empty I-Buffer is caused by sequential I-Fetching which has not been done on a timely basis.

The proposed solution is to overlap a Next Sequential I-Fetch with the two- cycle putaway by sharing the facilities between these two operations which are not required simultaneously. The nature of the cache operation which causes the two-cycle putaway must be understood first.

The two-cycle putaway for a store is due to the requirement of accessing the cache directories, DLAT (Directory Lookaside Table) and cache arrays concurrently during the first or C1 cache access cycle of a fetch operation. A store putaway operating in the second cycle prevents the pipelining of a subsequent fetch.

The NSIF (next sequential instruction fetch) requires only the cache arrays during the first cycle and the data bus during the second cycle of the store putaway, while the store operation requires the DLAT directory and bus during the first cycle, as shown in Fig. 1.

The ability of the NSIF to be accomplished without addressing, bus or directory lookup derives from the cache maintaining a NSIF pointer (NSIF PTR) which points to the line last a...