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Zero Condition Code Detection for Early Resolution of BCS and BCRS

IP.com Disclosure Number: IPCOM000049485D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 16K

Publishing Venue

IBM

Related People

Losq, JJ: AUTHOR [+2]

Abstract

The outcome of truly conditional BCs (Branch Condition) and BCRs (Branch on Condition Register) depends on the branch mask value and on the condition code (CC) setting. For many instructions, condition code setting involves a complex operation. For example, for arithmetic operations, the CC setting indicates if the result is greater than, less than, or equal to zero. For logical operations, it indicates whether the first operand is greater than, less than, or equal to the second operand. In general, the condition code is not available until the instruction has been through the E unit. Hence, the resolution of any branch that depends on the CC setting must wait until the CC setting instruction has been through the execution unit (E unit). In pipeline machines, this causes some delay, i.e.

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Zero Condition Code Detection for Early Resolution of BCS and BCRS

The outcome of truly conditional BCs (Branch Condition) and BCRs (Branch on Condition Register) depends on the branch mask value and on the condition code (CC) setting. For many instructions, condition code setting involves a complex operation. For example, for arithmetic operations, the CC setting indicates if the result is greater than, less than, or equal to zero. For logical operations, it indicates whether the first operand is greater than, less than, or equal to the second operand. In general, the condition code is not available until the instruction has been through the E unit. Hence, the resolution of any branch that depends on the CC setting must wait until the CC setting instruction has been through the execution unit (E unit). In pipeline machines, this causes some delay, i.e., the time needed to restart the pipeline on the correct branch path when the branch has been mispredicted (also referred to as a branch delay). Any scheme that provides for early CC setting will help by reducing this delay.

The BCs and BCRs do not test all CC settings with the same frequency. Most branches test for a zero condition code; whether or not the branch is taken depends only on whether the condition code is zero or non-zero. For most condition code setting instructions, the CC is set to zero if the result of the instruction is zero (or equality for the compare instructions). This is especially helpful for the compare and subtract instructions. One can determine whether the CC is zero by performing a simple bit by bit comparison of the operands. This can be performed in far less time and hardware than a full 32-bit subtraction.

The idea advanced here is to add to the processor the necessary logic to perform two 32 bit wide bit by bit compares. These compares will determine whether the CC is zero, far ahead of the time when the full condition code becomes available (at the end of the execution (E) cycle). The benefit is to be able to resolve conditional branches earlier, and thus reduce the delay associated with the incorrectly predicted branches.

The first comparator is used for the compare, subtract and condition code setting load instructions of the RR type. For these instructions, the two operands are available at the end of the decode (barring interlocks). So, one can, immediately after the decode, send the two operands through the comparator and, this way, determine if the condition code is going to be set to zero. This comparator can be physically close to the address adder and uses the same data paths. For these RR instructions, the address adder is not used (and thus the data paths are available).

The comparison of the two operands is done for the following instructions: CR hex 19 compare register

CLR hex 15 compare logical register

XR hex 17 exclusive OR register

LTR hex 12 load test register

LCR hex 13 load complement register

LNR hex 11 load negative register

LP...