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New Condition Code and Branch Architecture for High Performance Processors

IP.com Disclosure Number: IPCOM000049487D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Agerwala, TKM: AUTHOR

Abstract

The concept set forth allows maximum concurrency between the execution of architecturally separate instructions (fixed point scalar, floating point scalar, fixed point vector, floating point vector, etc.) with minimum burden on the hardware.

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New Condition Code and Branch Architecture for High Performance Processors

The concept set forth allows maximum concurrency between the execution of architecturally separate instructions (fixed point scalar, floating point scalar, fixed point vector, floating point vector, etc.) with minimum burden on the hardware.

Existing computer architectures, such as the IBM System/370 have a single condition code which is tested by branch instructions. In a high performance machine, with out of sequence execution, hardware must ensure that a branch instruction sees the logically correct condition code.

The architecture described herein allows this burden to be removed from the hardware, and also allows the use of advanced branch handling techniques in a natural manner. It is proposed that architecturally separate instructions (for example, fixed point scalar and floating point scalar) have separately architected condition codes. Usually, the number of such condition codes will be small (2 to
8). New instructions, EVAL CC(i), are architected. EVAL CC, specifies the condition code class and the condition to be tested for. The result is a true/false indication. Conditional branch instructions specify the architectural class of the CC and the target address. A branch without a preceding EVAL is treated as an NOP. An implementation of this approach is described below.

An I-unit does instruction fetching and has a branch handler. A predecoder dispatches instructions to other units based on architectural class. Each class of instructions i has its own unit i. A complete decode and execution is performed in these units. The local condition code CC(i) for class i is updated...