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VLSI Switching-Circuit Failure Testing

IP.com Disclosure Number: IPCOM000049489D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 4 page(s) / 39K

Publishing Venue

IBM

Related People

Roth, JP: AUTHOR

Abstract

In some VLSI technologies it is possible to realize functions by means of switching circuits as well as logic networks; in particular for field effect transistors (FETs) the switching realization is substantially faster. Logic network techniques, notably the D-algorithm, have been extensively developed and used for failure testing. Yet, no such effective algorithms appear for switching circuits. Such a method is described here.

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VLSI Switching-Circuit Failure Testing

In some VLSI technologies it is possible to realize functions by means of switching circuits as well as logic networks; in particular for field effect transistors (FETs) the switching realization is substantially faster. Logic network techniques, notably the D-algorithm, have been extensively developed and used for failure testing. Yet, no such effective algorithms appear for switching circuits. Such a method is described here.

In large-scale integration (LSI) and very large-scale integration (VLSI) technologies, it is possible to realize functions both by logic-technology, and indeed the switching-circuit realization is substantially faster than the logic realization (1). While there are methods, notably the D-algorithm (2), for testing- for-failure in logic circuits, as yet there do not exist effective algorithms for testing-for-failures for such realizations: this method is described herein.

A switching circuit S consists of a nondirected graph; each node of the graph is uniquely labelled, a, b, c,..., with each branch associated with a binary variable A,B,C,..., or its negation, denoted A,B,C.... At least one pair of nodes is
designated a terminal-pair, p, q; the switching circuit together with its terminal pair define a Boolean function.

The names of the nodes a,b of a branch together with the association of binary variable A (or A) define a unique label a,A,b (or a,A,b), with b,A,a (or b,A,a) being considered as the same or equivalent label. If two branches connect two given nodes and have the same variable, A or both A, attached, then one of them may be eliminated from the specification; S together with a terminal pair define a Boolean function (3). Essentially, each acyclic path between the terminal nodes determines a logical product of the variable attached to the branches along the path, and the logical sum of these products defines the function.

Each branch with its variable label A or A may be thought of as a switch controlled by A or A. When A=l, the switch is closed and there is a path through the switch connecting its nodes. When A=0, the switch is open and there is no path through the switch between its nodes. The operation occurs inversely for the branch controlled by A.

The switching circuit S (Fig. 1) consists of four nodes a, b, c, d and five branches a,b; a,c; b,d; c,d; b,c controlled by variables A, B, C, D, E.

Fig. 1 is a (bridge) switching circuit with a and b as terminal nodes. The function performed by the switching circuit is f=AC BD AED BEC corresponding to the four acyclic paths between a and b; here, "I" stands for "OR" and the concatenation of variables for "AND".

Each branch of a switching circuit may fail by being fixed (or stuck) open or closed. In either case the terminal function will be modified, if there is no redundancy, and, given an appropriate input pattern, the assignment of values to each of the variables, the switching circuit may produce an error....