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Reducing VLSI Diagnosis to LSI Diagnosis

IP.com Disclosure Number: IPCOM000049490D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 4 page(s) / 28K

Publishing Venue

IBM

Related People

Kurtzberg, JM: AUTHOR [+2]

Abstract

Diagnosis of failures has been a major problem for LSI (large-scale integration). Presently, on the order of 50,000 circuits can be handled for test generation, with running time and storage growing exponentially (1). Test generation for VLSI (very large-scale integration) promises to be very much more difficult. Proposed here is a method for subdivision of VLSI logic, say, a million circuits, into LSI pieces plus feasible means for independent access to the LSI subdivisions for test purposes. In effect, this reduces VLSI diagnosis to LSI diagnosis.

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Reducing VLSI Diagnosis to LSI Diagnosis

Diagnosis of failures has been a major problem for LSI (large-scale integration). Presently, on the order of 50,000 circuits can be handled for test generation, with running time and storage growing exponentially (1). Test generation for VLSI (very large-scale integration) promises to be very much more difficult. Proposed here is a method for subdivision of VLSI logic, say, a million circuits, into LSI pieces plus feasible means for independent access to the LSI subdivisions for test purposes. In effect, this reduces VLSI diagnosis to LSI diagnosis.

VLSI would involve a million circuits or more. The problem of testing VLSI presents an order of magnitude of increase in difficulty over LSI, where one is able to handle 50,000 circuits. What is given here is a method of segmenting a VLSI design into a number of LSI subdivisions together with means for testing the subdivisions directly.

The method of subdivision: Initially, there is subdivision for each primary output (PO) and primary input (PI) of the VLSI logic, which is assumed to be regular (1). For each PO there is included in the subdivision all circuits having this PO as an output, and similarly for PIs. If two subdivisions have a common PO or PI, then merge these subdivisions unless their combined number exceeds a prescribed bound B, in which case they are not merged.

At any stage of subdivision construction, the inputs and outputs of each subdivision are examined and adjoined to the subdivision those which introduce a minimum of new circuits; if two subdivisions have common I/Os, then these are merged provided the number of circuits does not exceed a prescribed bound. Method of implementation for testing (1)

For testing the inputs to each subdivision, as set forth in the figure, a normal input is controlled by a register input R. R and the normal input commonly feed an AND circuit A. When R=1, the normal input flows through the OR to its T. However, when the test input is activated, by having R=0 and S=1 then the test input is channeled through the OR to output T. The signal from register R can be fanned out to each such normal input, so that it does not have to be duplicated, but the register S must be unique for each test input.

In general, a shift register, emanating from a given input pin, will supply values to the test register S(3). It is clear that only the subdivisions need be diagnosed by means of this method of implementation for testing.

A key factor in the implementation of the VLSI diagnosis is the means for partitioning the logic. Three methods for so doing are described below.

The first is a natural means, coming from a high-level description; PL/R (1) is a high-level logic language in which to describe hardware; it is isomorphic to a small subset of PL/I. RTRAN is a compiler which accepts PL/R and produces a hardware realization.

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The implementation is such that it preserves macros, i.e., the logic defining,...